The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

Hichem Ferhati, Fayçal Djeffal and Toufik Bentrcia
Beilstein J. Nanotechnol. 2018, 9, 1856–1862. https://doi.org/10.3762/bjnano.9.177

Cite the Following Article

The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability
Hichem Ferhati, Fayçal Djeffal and Toufik Bentrcia
Beilstein J. Nanotechnol. 2018, 9, 1856–1862. https://doi.org/10.3762/bjnano.9.177

How to Cite

Ferhati, H.; Djeffal, F.; Bentrcia, T. Beilstein J. Nanotechnol. 2018, 9, 1856–1862. doi:10.3762/bjnano.9.177

Download Citation

Citation data can be downloaded as file using the "Download" button or used for copy/paste from the text window below.
Citation data in RIS format can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Zotero.

Presentation Graphic

Picture with graphical abstract, title and authors for social media postings and presentations.
Format: PNG Size: 317.0 KB Download

Citations to This Article

Up to 20 of the most recent references are displayed here.

Scholarly Works

  • Odey, M. O.; Gulack, A. O.; Imojara, B.; Benjamin, I. Surface tailoring of Graphene via silicon co-doping with Group 15 Elements for the Detection of Ochratoxin (OTX): An Insilco Investigation. Materials Today Communications 2024, 40, 109713. doi:10.1016/j.mtcomm.2024.109713
  • Das, D.; Chakraborty, U.; Borah, P. Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor. Semiconductor Science and Technology 2024, 39, 85005–085005. doi:10.1088/1361-6641/ad5466
  • Mann, R.; Chaujar, R. Self-Consistent LCAO Based DFT Analysis of High-k Spacers and its Assessment on Gate-Stacked NCFET for Improved Device-Circuit Performance. Silicon 2024, 16, 5185–5197. doi:10.1007/s12633-024-03074-w
  • Thakur, A.; Dhiman, R.; Wadhwa, G.; Bhandari, S. Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2024, 37. doi:10.1002/jnm.3217
  • Odey, M. O.; Gulack, A. O.; Imojara, B.; Benjamin, I. Surface Tailoring of Graphene Nanomaterials Via Silicon Codoping with Group 15 Sensors for Ochratoxin (Otx): Insight from a Computational Study. Elsevier BV 2024. doi:10.2139/ssrn.4824770
  • Gayen, S.; Tewari, S.; Chattopadhyay, A. A Judicious Exploitation of Electrical Characteristics of a Unique GeSn TFET With Corner-Point for Sensing S-Protein Biomarker. IEEE Transactions on Nanotechnology 2024, 23, 467–473. doi:10.1109/tnano.2024.3409055
  • Thakur, A.; Dhiman, R. Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain. AEU - International Journal of Electronics and Communications 2023, 167, 154668. doi:10.1016/j.aeue.2023.154668
  • Das, A.; Rewari, S.; Kanaujia, B. K.; Deswal, S. S.; Gupta, R. S. Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET. Physica Scripta 2023, 98, 74005–074005. doi:10.1088/1402-4896/acde16
  • Thakur, A.; Dhiman, R.; Wadhwa, G. Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study. Nano 2023, 18. doi:10.1142/s1793292023500315
  • Kumar, K.; Kumar, A.; Kumar, V.; Sharma, S. C. Comparative Investigation of Band Gap and Gate Metal Engineered Novel Si0.2Ge0.8/GaAs Charge Plasma-Based JLTFET for Improved Electrical Performance. Silicon 2023, 15, 4689–4702. doi:10.1007/s12633-023-02387-6
  • Kumar, K.; Kumar, A.; Sharma, S. C. Electrical performance improvement of charge plasma-based junctionless TFET using novel coalescence of SiGe/GaAs and heterogeneous gate dielectric. Applied Physics A 2022, 129. doi:10.1007/s00339-022-06309-y
  • Kumar, K.; Kumar, A.; Mishra, V.; Sharma, S. C. Implementation of Band Gap and Gate Oxide Engineering to Improve the Electrical Performance of SiGe/InAs Charged Plasma-Based Junctionless-TFET. Silicon 2022, 15, 1303–1313. doi:10.1007/s12633-022-02111-w
  • Baruah, K.; Baishya, S. Performance Assessment of Ge-Source Double-Gate PNPN TFET Based Biosensor. In 2022 IEEE Region 10 Symposium (TENSYMP), IEEE, 2022; pp 1–6. doi:10.1109/tensymp54529.2022.9864500
  • Eliwy, M.; Elgamal, M.; Shaker, A.; Fedawy, M. Impact of gate-on-drain overlap on the electrical characteristics of TFETs: Role of oxide material and drain spacer. Pramana 2022, 96. doi:10.1007/s12043-022-02341-y
  • Sharma, S.; Chaujar, R. Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET. AEU - International Journal of Electronics and Communications 2021, 133, 153669. doi:10.1016/j.aeue.2021.153669
  • Ferhati, H.; Djeffal, F.; Drissi, L. B. Performance assessment of a new infrared phototransistor based on JL-TFET structure: Numerical study and circuit level investigation. Optik 2020, 223, 165471. doi:10.1016/j.ijleo.2020.165471
  • Shaw, N.; Mukhopadhyay, B.; Sen, G. Study of the electrical parameters of a dual-material double-gate TFET using a strained type II staggered Ge1−x−ySixSny/Ge1−a−bSiaSnb heterojunction. Journal of Computational Electronics 2020, 19, 1433–1443. doi:10.1007/s10825-020-01540-3
  • Ferhati, H.; Djeffal, F.; Bentrcia, T. ICIST - Novel Infrared phototransistor based on Junctionless TFET design: Numerical Analysis and Performance Assessment. In Proceedings of the 10th International Conference on Information Systems and Technologies, ACM, 2020; pp 1–5. doi:10.1145/3447568.3448545
  • Das, D.; Chakraborty, U. A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps. Silicon 2020, 13, 787–798. doi:10.1007/s12633-020-00488-0
  • Yadav, R.; Dan, S. S.; Vidhyadharan, S.; Hariprasad, S. Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node. Journal of Computational Electronics 2020, 19, 291–303. doi:10.1007/s10825-019-01440-1
Other Beilstein-Institut Open Science Activities