Impact of contact resistance on the electrical properties of MoS₂ transistors at practical operating temperatures

Introduction

Transition metal dichalcogenides (TMDs) are compound materials formed by the Van der Waals stacking of MX₂ layers (where M = Mo, W, etc., i.e., a transition metal, and X = S, Se, Te, i.e., a chalcogen atom). Among the large number of existing layered materials [1], TMDs are currently attracting increasing scientific interest due to some distinct properties, such as the presence of a sizable bandgap in their band structure. As an example, MoS₂ (the most studied among TMDs due to its high abundance in nature and relatively high stability under ambient conditions) exhibits an indirect bandgap of ≈1.3 eV in the case of few layers and bulk material and a direct bandgap of ≈1.8 eV in the case of a single layer. These properties make MoS₂ an interesting material for the next generation of electronics and optoelectronics devices [2]. As an example, field effect transistors with very interesting performance in terms of the on/off current ratio (10⁶–10⁸) and low subthreshold swing (≈70 meV/decade) have been demonstrated using single [3] and multilayers of MoS₂ [4].

MoS₂ thin films, obtained either by cleavage from the bulk material or by chemical vapor deposition, are typically unintentionally n-type doped. Since well-assessed methods for doping enrichment of MoS₂ under source/drain contacts are still lacking, MoS₂ transistors are mostly fabricated by deposition of metals directly on the unintentionally doped material, resulting in the formation of Schottky contacts. Experimental investigations showed that both low work function (e.g., Sc, Ti) and high work function (e.g., Ni, Pt) metals mostly exhibit a Fermi level pinning close to the conduction band of MoS₂ [5], resulting in a Schottky barrier height (SBH) for electrons typically ranging from 0.1 to 0.3 eV. The origin of this Fermi level pinning is currently a matter of investigation and a crucial role seems to be played by nanoscale defects/inhomogeneities at the metal/MoS₂ interface [6,7].

The presence of this small but not negligible Schottky barrier at source/drain contacts certainly has a strong impact on the electrical characteristics of MoS₂ transistors in the subthreshold regime [5]. In addition, the resulting source/drain contact resistance, R_C, can also have a significant influence on the electrical properties of the device in the on-state, i.e., above the threshold voltage (V_th). In particular, R_C is expected to affect, to some extent, the values of V_th and of the field effect mobility μ extracted from the transfer characteristics (drain current, I_D, vs gate bias, V_G) of the device and of the on-resistance (R_on) extracted from the output characteristics (drain current, I_D, vs drain bias, V_DS). Clearly, all these parameters (V_th, μ, and R_on) have their own dependence on the temperature, and their combination results in the device electrical characteristics at a fixed measurement condition. Hence, to gain a deeper understanding of the behavior of MoS₂ transistors for real applications, a temperature-dependent characterization of the main electrical parameters under practical operating conditions is mandatory. A temperature range from room temperature to 400 K is a realistic range for device operation in circuits/systems, taking into account the heating effect they undergo due to inefficient heat dissipation. However, to date, only a limited number of papers have focused on the high temperature behavior of MoS₂ transistors [8,9].

In this paper, we report a detailed temperature dependent investigation of multilayer MoS₂ transistors with Ni source/drain contacts, focusing on the role played by the contact both in the subthreshold regime and above the threshold voltage. In contrast to other literature works, mainly focused on the use of low work function contacts (such as Sc or Ti) to minimize the effect of contact resistance in n-type MoS₂ FETs [5], we focused on a high work function metal such as Ni in this paper in order to evaluate the impact of Ni/MoS₂ contact resistance on the device field effect mobility μ and threshold voltage V_th. The interest on Ni was also motivated by the recently demonstrated possibility to achieve MoS₂ FETs with ambipolar behavior by performing a temperature-bias annealing processes on as-deposited Ni contacts [10]. In the following, the temperature dependence of μ, V_th and R_C in the range from 298 to 373 K was determined and the physical mechanisms of these dependences were discussed.

Results and Discussion

Back-gated transistors have been fabricated using multilayer MoS₂ flakes (with thickness ranging from ≈40 to ≈50 nm) exfoliated from bulk molybdenite crystals onto a highly doped Si substrate covered with 380 nm thick, thermally grown SiO₂. Such relatively thick MoS₂ samples have been chosen since it has been reported that the electrical properties (μ, V_th) of simple back-gated transistors fabricated with multilayer MoS₂ are much less affected by the effect of the external environment (water/oxygen) [9] with respect to single or few layer devices [11], for which encapsulation is instead required to achieve good electrical performance [3].

Furthermore, as reported in the literature, carrier mobility is only slightly dependent on MoS₂ thickness for transistors fabricated on ≈20 to ≈70 nm thick flakes, whereas stronger variations are observed for thinner flakes, with the largest mobility values obtained for thicknesses ranging from 6 to 12 nm [5].

The experiments discussed in this paper have been carried out on a set of ten FETs fabricated on the same substrate. For consistency, the reported temperature-dependent analysis has been carried out on one of the transistors from this set of devices. Figure 1a shows a schematic representation including an optical image of a MoS₂ transistor with the SiO₂/Si backgate and Ni/Au source and drain contacts. An atomic force microscopy image (Figure 1b) and the corresponding height linescan (Figure 1c) of the MoS₂ flake on the SiO₂ substrate are also reported, showing ≈40 nm flake thickness.

The transfer characteristics (I_D−V_G) measured at a low fixed drain bias (V_DS = 0.1 V) on this device at different temperatures from 298 to 373 K are reported in Figure 2 both on a semilogarithmic scale (Figure 2a) and on a linear scale (Figure 2b). Clearly, the linear scale plot allows the current transport above the threshold voltage (V_th) to be studied, whereas the semilog scale plot allows for a better visualization of transport in the subthreshold regime. In the following two sections, a detailed analysis of the characteristics in the subthreshold and above-threshold regime will be reported and the device electrical parameters will be extracted. In particular, the Ni/MoS₂ Schottky barrier height and the flat band voltage (V_FB) will be evaluated from the temperature-dependent analysis of the subthreshold I_D−V_G curves, whereas the temperature behavior of V_th and μ will be obtained from the curves above the threshold.

Subthreshold behavior

The semilog scale I_D−V_G characteristics (Figure 2a) measured at 298 K exhibit a current variation of more than six orders of magnitude in the bias range from V_G = −55 V to 0 V. This current variation is significantly reduced with increasing the temperature from 298 to 373 K, especially due to the strong increase of current with the temperature at large negative bias.

This is better highlighted in Figure 3a, where the I_D−V_G characteristics in the gate bias range from −55 to −35 V and at different temperatures from 298 to 373 K have been reported. Such strong dependence of I_D on T suggests that current transport in the subthreshold regime is dominated by thermionic current injection through the reverse biased source/MoS₂ Schottky contact, according to the relation [5], where Φ_B(V_G) is the effective Schottky barrier height (SBH), modulated by the gate bias V_G. To verify this, for each V_G an Arrhenius plot of I_D/T² vs 1000/T is reported in Figure 3b. A nice linear dependence was observed for all the V_G in the considered bias range. The effective SBH values Φ_B, obtained from the slope of the linear fit of the Arrhenius plot in Figure 3b are reported in Figure 3c as a function of V_G. The schematic band diagrams corresponding to the different transistor operation regimes, i.e., depletion (i), flat band (ii) and accumulation (iii), are also illustrated in the inserts of Figure 3c.

In the depletion regime (Figure 3c (i)), the applied gate bias induces an upward band bending, ψ, in MoS₂ at the interface with the SiO₂ gate insulator. The experimentally evaluated SBH is found to depend linearly on V_G. This dependence can be fitted with the relation where Φ_B(V_FB) is the effective SBH at the flat band voltage and the term ψ = γ(V_G−V_FB) is the upward band bending. The slope γ indicates the modulation efficiency of Φ_B by the gate bias. It depends on the SiO₂ layer capacitance, C_ox = ε₀ε_ox/t_ox ≈ 9.1 × 10⁻⁵ F/m² (ε₀ is the vacuum dielectric constant, ε_ox = 3.9, t_ox = 380 nm, the permittivity and the thickness of the SiO₂ film, respectively), on the capacitance of the MoS₂ depletion region, C_s, as well as on the capacitance associated with MoS₂/SiO₂ interface traps, C_it [5]. In the depletion regime, the current transport in the transistor is ruled by thermionic emission (TE) of electrons from the source contact to the channel.

The effective SBH Φ_B and, hence, the band bending ψ = Φ_B(V_G)−Φ_B(V_FB) is found to decrease linearly moving toward positive V_G values. The flat band voltage V_FB corresponds to the gate bias for which ψ = 0 (see (ii) in Figure 3b), whereas for V_G > V_FB the band bending ψ < 0 (see (iii) in Figure 3b), i.e., the channel starts to accumulate electrons. In the accumulation regime, current injection in the channel is ruled by thermionic field emission (TFE) through the source triangular barrier. The TFE mechanism yields a reduced effective SBH with respect to the constant Φ_B value (red dashed line in Figure 3c) that would be expected if only TE over the barrier would occur. As a guide for the eye, the SBH dependence on V_G in the accumulation regime has been fitted with a blue line in Figure 3c. Hence, V_FB = −39.6 V can be experimentally determined as the bias corresponding to the intercept between the two linear fits [5]. The corresponding SBH value Φ_B(V_FB) = 0.18 eV represents the “real” (i.e., gate bias independent) value of the Ni/MoS₂ Schottky barrier.

The experimental V_FB for the MoS₂ transistor exhibits a large negative value, as reported in other literature works [12]. Such a result has been ascribed to donor-like interface trap states (positively charged when empty) between the SiO₂ and MoS₂ [13,14]. In order to evaluate the amount of this positive charge at the interface, it is worth comparing the experimental value with the one deduced from theoretical expression of the flat band voltage (V_FB,id) of an ideal metal-oxide-semiconductor field effect transistor (i.e., without fixed or interface charges). V_FB,id is expressed as [15]:

where W_M is the work function of the gate material (4.05 eV for the n⁺-doped Si back gate in our transistor), χ is the semiconductor electron affinity (4.2 eV for MoS₂), N_D is the semiconductor doping concentration (on the order of 10¹⁶ cm⁻³ in unintentionally doped MoS₂) and n_i is the intrinsic carrier concentration (for MoS₂, cm⁻³). According to this expression a low value of V_FB,id slightly varying with the T (from −0.35 V at 298 K to −0.42 V at 273 K) would be expected for our device. The negative shift of the experimental V_FB with respect to V_FB,id can be accounted for by the presence of a net positive charge density at the interface with SiO₂ that can be evaluated as C_ox(V_FB−V_FB,id)/q ≈ 2.2 × 10¹² cm⁻².

In the following section, the device transfer characteristics above the threshold will be analyzed to extract the threshold voltage and mobility.

Transfer characteristics above threshold

The linear scale transfer characteristics (Figure 2b) show very low current below a threshold voltage (V_th) and a nearly linear increase of I_D vs V_G above V_th. Two effects can be observed from the comparison of the I_D−V_G curves at increasing temperatures, i.e., (i) a negative shift of the threshold voltage and (ii) a decrease of the I_D−V_G curve slope in the linear region above V_th. The origin of these two effects will be discussed more in detail later on. Interestingly, as a result of these two competing effects, the I_D−V_G characteristics tend to cross nearly at the same gate bias V_G = −21 V (see details in the insert of Figure 2b). This bias condition can be interesting for some applications where it is desirable that the device performance does not depend significantly on the temperature (dI_D/dT ≈ 0).

Figure 2c shows the transconductance g_m vs V_G curves calculated by differentiation (g_m = dI_D/dV_G) of the I_D−V_G characteristics in Figure 2b. In the considered bias range, all the curves exhibit an increase of g_m with V_G up to a maximum value, followed by a decrease of g_m. The maximum transconductance value (g_m,max) is found to decrease with increasing temperature. Furthermore, a rigid shift of the g_m–V_G curves toward negative gate bias values is observed with increasing T.

From the linear scale transfer characteristics and the transconductance, two key electrical parameters for transistor operation, i.e., the threshold voltage (V_th) and the field effect mobility (μ), are typically evaluated. Figure 4a shows a linear scale plot of I_D (left axis) and of the transconductance g_m (right axis) at V_DS = 0.1 V and T = 298 K. The field effect mobility in the linear region, μ_lin, of the transfer characteristics is typically extracted from the transconductance using the following formula where L and W are the channel length and width, respectively, and C_ox the SiO₂ gate capacitance. For our device with L/W = 7 μm/25 μm and C_ox ≈ 9.1 × 10⁻⁵ F/m², the evaluated mobility from the maximum transconductance value g_m,max was μ_lin = 31.75 cm²V⁻¹s⁻¹, as indicated in Figure 4a. A method for evaluating V_th consists of drawing the tangent line to the I_D−V_G curve at the bias (V_G,max) corresponding to g_m,max and taking the intercept with the I_D = 0 baseline [16], as shown in Figure 4a.

This procedure can be explained by simple geometrical considerations. In the linear region of the transfer characteristics, I_D can be expressed as [14]:

Hence, it results that I_D,max = g_m,max(V_G,max−V_th) and the threshold voltage can be calculated as

As a matter of fact, for the evaluation of V_th,lin and μ_lin based on Equation 2 the contribution of the contact resistance is assumed to be zero. However, as deduced from the analysis of the subthreshold characteristics, a Schottky barrier is associated to the source/drain contacts with MoS₂, which is also expected to result in a non-negligible contact resistance, R_C. The value of the contact resistance above the threshold and its temperature dependence will be estimated in the last section of this paper from the analysis of the on-resistance (R_on) extracted from the device output characteristics (I_D−V_DS) at low V_DS. Here, we want to discuss how R_C can influence the evaluation of μ and V_th from the transfer characteristics.

In order to take into account the role of R_C, V_DS can be replaced by V_DS−I_DR_C in Equation 2, and solving by I_D, the following expression for I_D is obtained:

where μ₀ and V_th,0 represent the values of the mobility and threshold voltage corrected by the effect of R_C. As a consequence, the transconductance g_m = dI_D/dV_G can be expressed as:

Noteworthy, the ratio is independent of R_C. A plot of I_D/g_m^1/2 vs V_G is reported in Figure 4b. The corrected value of the field effect mobility (μ₀ = 35.48 ± 0.25 cm²V⁻¹s⁻¹) can be calculated from the slope of the linear fit of these data, whereas the threshold voltage (V_th,0 = −34.99 ± 0.19 V) can be obtained from the intercept with the x axis. It is worth noting that the mobility value μ₀ after correction for the contact resistance is more than 10% higher than the value estimated without any correction, whereas the threshold voltage V_th,0 after correction is only 1% higher than the value estimated without accounting for R_C. This indicates that the underestimation of the mobility neglecting the contact resistance effect can be quite relevant, whereas the threshold voltage is less affected by R_C. By repeating this procedure for all the measured characteristics reported in Figure 2b,c, the temperature dependence of the mobility (μ_lin and μ₀), threshold voltage (V_th and V_th,0) in the considered temperature range has been evaluated, as illustrated in Figure 5a,b, respectively.

Both μ_lin and μ₀ were found to decrease as a function of T with a similar dependence 1/T^α, with α = 1.5 ± 0.2 in the case of μ_lin and α = 1.4 ± 0.3 in the case of μ₀. Such a dependence of μ ≈ 1/T^α with α > 1 indicates that the main mechanism limiting the mobility of electrons in the multilayer MoS₂ channel in this temperature range is scattering by optical phonons, as reported by other experimental and theoretical investigations [4]. Instead, electron mobility was found to be limited by Coulomb scattering by charged impurities only at lower temperatures (<100 K) [4]. Noteworthy, scattering by charged impurities at the interface with the substrate results in the dominant mechanism for another well-studied 2D material, graphene, even at room temperature and higher temperatures [17,18].

In Figure 5b, the threshold voltage V_th exhibits a negative shift of about 6 V with increasing the temperature from 298 to 273 K. For convenience, the difference V_th−V_FB is also reported in Figure 5b, right scale. It is useful to compare the experimental temperature dependence of V_th with the expected theoretical variation with temperature, in order to understand which are the relevant physical parameters ruling this behavior.

For an ideal transistor (without interface states) operating under accumulation conditions, the shift between the threshold voltage V_th,id and the flat band voltage V_FB,id can be expressed as:

where ψ_th is the downward (negative) band bending at the threshold (as illustrated in the band diagram (iii) of Figure 3c, and N_s(ψ_th) is the electron density in the channel at ψ_th

where is the Debye length. The band bending ψ_th can be evaluated assuming that the electron density in the channel at the threshold corresponds to N_s(ψ_th) = tN_D, where N_D is the uniform doping concentration in the MoS₂ thin film and t its thickness. Assuming N_D = 10¹⁶ cm⁻³ for our unintentionally doped MoS₂, we obtain N_s ≈ 4 × 10¹⁰ cm⁻². Furthermore, a value of ψ_th ranging from approximately −34 meV (at T = 298 K) to −39 meV (at T = 373 K) can be estimated from the dependence of N_s on ψ_th in Equation 6. Under these assumptions, V_th,id−V_FB,id ≈ 0.7 eV (nearly independent of T) can be estimated, as indicated in Figure 5b (blue dashed line).

In order to account for the large change of V_th with temperature, the role of interface states at SiO₂/MoS₂ interface must be considered. The difference between the experimental V_th−V_FB and theoretical V_th,id−V_FB,id can be described by a term ΔV_it = qN_it/C_ox, where N_it is the density of trapped/detrapped electrons by SiO₂ interface traps. These interface traps exhibit a donor like behavior, i.e., they are positively charged above the Fermi level (when they are empty) and neutral below the Fermi level (when they are filled by electrons) [13]. Hence, electron trapping results in a neutralization of the interface states, resulting in a positive shift of V_th with respect to V_FB (i.e. ΔV_it > 0). On the contrary, detrapping of electrons from these states results in an increase of the positive charge and, hence, in ΔV_it < 0.

From the experimental data in Figure 5b, trapped electron densities N_it = 2 × 10¹¹, 1 × 10¹¹, and 2 × 10¹⁰ cm⁻² are estimated at 298, 323, and 348 K, respectively, whereas a detrapped electron density N_it = 1.3 × 10¹¹ cm⁻² is obtained at 373 K (see Figure 5c). Electron trapping and detrapping at MoS₂/SiO₂ interface have been shown to be thermally activated processes [13]. Hence, for a given interface trap distribution D_it close to the MoS₂ conduction band, N_it can be expressed as

where P_tr(T) and P_det(T) are the trapping and detrapping probabilities, respectively [13]. The experimentally found temperature dependence of N_it can be explained as follows. As T increases, the shift of the Fermi energy E_F with respect to E_C increases as

resulting in a change of the integration range in Equation 7. Furthermore, the difference P_tr(T)−P_det(T) can change with T. The dependence of N_it on E_F is also illustrated in Figure 5c. It is consistent with a decrease of D_it with increasing E_F−E_C. Furthermore, at 373 K, it can be argued that the P_det becomes higher than P_tr, resulting in a negative value of N_it.

Output characteristics

Figure 6 shows the output characteristics I_D−V_DS for different gate bias values ranging from V_G = −56 to 0 V (with steps ΔV = 4 V) measured at different temperatures, i.e., (a) 298 K, (b) 323 K, (c) 348 K and (d) 373 K. For all the V_G values, I_D exhibits a linear increase with V_DS at low drain bias (V_DS << V_G−V_th), whereas it deviates from the linear behavior at larger V_DS. In particular, current saturation is achieved whenever the condition V_DS > V_G−V_th is reached. By comparing the output characteristics measured at the different temperatures with the same V_G values, it is evident that both the slope of the I_D−V_DS curves in the linear region and the saturation current value decreases with increasing T.

The reciprocal of the I_D−V_DS curves slope in the linear region at low V_DS is the device on-resistance R_on, which can be expressed as:

where R_C is the source and drain contact resistance and R_ch the channel sheet resistance, which depends inversely on (V_G−V_th), according to Equation 2.

Figure 7a reports the plots of R_on vs 1/(V_G−V_th,lin) extracted from the I_D−V_DS characteristics in Figure 6 at the different temperatures. The linear fit of the data was performed for the four temperatures and, from the intercept with the vertical axis, the value of the contact resistance R_C was estimated. The behavior of R_C vs T is reported in Figure 7b, indicating an increase of R_C T^α, with α = 3.1 ± 0.3.

Finally, the behavior of the output characteristics at high V_DS is discussed. Figure 8a shows the I_D−V_DS characteristics measured at T = 298 K. The V_G−V_th value for each curve is indicated. It can be observed that the current saturation regime (i.e., I_DS independent of V_DS) is reached only for V_G−V_th < 20 V, corresponding to an accumulated electron density in the channel N_s < 1.1 × 10¹² cm⁻². For V_G−V_th > 20 V, saturation is not reached.

In the saturation condition, I_D is only a quadratic function of V_G−V_th [14]:

where μ_sat is the mobility value under saturation conditions and the term B is the so-called body coefficient, which depends on the gate oxide capacitance, on the doping concentration in the film and on the temperature:

For thin gate dielectrics and low doping in the film, B can be approximated to 1, but for thick dielectrics and high doping its value can be significantly higher. In the case of our device with C_ox = 9.1 × 10⁻⁵ F/m and assuming a MoS₂ doping N_D ≈ 1 × 10¹⁶ cm⁻³, B can range from ≈2.97 to ≈3.12 in the considered temperature range. In Figure 8b, I_D^1/2 at V_DS = 20 V is reported as a function of V_G−V_th, showing a linear behavior. According to Equation 9, the mobility under saturation condition can be evaluated from the slope m of the fit, as . By repeating this procedure for all the output characteristics measured at the different temperatures, the behavior of μ_sat as a function of T can be obtained. The main error source in the estimation of μ_sat is related to the fact that the doping concentration N_D and, hence, the coefficient B is not exactly known. Noteworthy, the values of μ_sat in Figure 8c, estimated assuming N_D ≈ 1 × 10¹⁶ cm⁻³, are very close to those evaluated from the linear region of the transfer characteristics (see Figure 5a) and exhibit a similar temperature dependence. This also confirms that the assumption for the doping concentration is correct.

Conclusion

In conclusion, a temperature dependent investigation of back-gated multilayer MoS₂ transistors with Ni source/drain contacts in the range from T = 298 to 373 K has been performed. The SBH Φ_B ≈ 0.18 eV of the Ni/MoS₂ contact was evaluated from the analysis of the transfer characteristics I_D−V_G in the subthreshold regime. The resulting R_C associated with the SBH was determined by fitting the R_on dependence on 1/(V_G−V_th) extracted from the device output characteristics I_D−V_DS at low V_DS. An increase of R_C T^3.1 was demonstrated. The impact of R_C on the values of μ and V_th values was determined, showing an underestimation of μ by more than 10% if the effect of R_C is neglected, whereas the influence of R_C on the estimated value of V_th is only 1%. Furthermore, the temperature dependence of μ and V_th was investigated, showing a decrease of μ ≈ 1/T^α with α = 1.4 ± 0.3 (indicating scattering by optical phonons as the limiting mechanism), and a negative shift of V_th by about 6 V with increasing T. The role played by electron trapping at the MoS₂/SiO₂ interface to explain such a large V_th shift was discussed.

Experimental

Back-gated transistors were fabricated using MoS₂ flakes exfoliated from molybdenite bulk crystals (supplier SPI [19]) with thicknesses ranging from ≈40 to ≈50 nm and transferred onto a highly doped n-type Si substrate covered with 380 nm of thermally grown SiO₂. An accurate sample preparation protocol has been adopted for controlled quality of the MoS₂/SiO₂ interface, as this is crucial to achieve reproducible electrical behavior of the devices. In particular, thermo-compression printing using a Karl-Suss nanoimprint device with fixed temperature and pressure conditions [20,21] has been employed to transfer the exfoliated MoS₂ flakes onto the SiO₂ surface that was previously cleaned using solvents and a soft O₂ plasma treatment. Finally, source and drain contacts were obtained by deposition and lift-off of a Ni(50 nm)/Au(100 nm) bilayer.

The temperature-dependent electrical characterization in the range from 298 to 373 K was performed using a Cascade Microtech probe station with an Agilent 4156b parameter analyzer. All the measurements were carried out in dark conditions and under nitrogen flux.