Beilstein J. Nanotechnol.2024,15, 713–718, doi:10.3762/bjnano.15.59
excellent improvement in TFETs, an on-current of 1.00 × 10−5 A/μm, an Ion/Ioff ratio of 7.14 × 1011, and a threshold voltage of 0.28 V.
Keywords: dual low-work-function live strip (DLWLS); low-k dielectric spacer; low-work-function live strip (LWLS); Millercapacitance; molybdenum; subthreshold swing (SS
thermionic emission as the carrier injection mechanism [3]. Band-to-band tunneling enables TFETs to have SS < 60 mV/dec [4][5][6][7]. The gate-to-drain capacitance (Cgd) effect (Millercapacitance effect) has an impact on TFET performance. Unwanted effects such as overshoot/undershoot in the inverter
characteristics grow when Cgd rises [8]. The gate-to-drain capacitance increases as a result of a high-k material in the drain region [9]. Ambipolar leakage and Millercapacitance are two drawbacks of TFETs. The Millercapacitance can be reduced through oxide overlap and low-bandgap materials [10].
The solution
PDF
Figure 1:
Cross-sectional schematic of the proposed VTFET with DLWLS + spacer device.